Title:
HETEROJUNCTION BIPOLAR TRANSISTOR
Document Type and Number:
Japanese Patent JP3314183
Kind Code:
B2
Abstract:
PURPOSE: To prevent the deterioration of the current amplification factor of the title transistor by suppressing an increase in base current with time during the operation of the transistor.
CONSTITUTION: An n-type GaAs collector buffer layer 1, undoped GaAs collector layer 2, indium-added carbon-doped p-type GaAs base layer 13, n-type A0.3Ga0.7As emitter cap layer 5 are successively formed on a semi-insulating GaAs substrate S by epitaxial growth. After the layers are formed into mesa-type, an emitter electrode 6 composed of WSi/W, base electrode 7 composed of Ti/W, and collector electrode 8 composed of AuGe/Ni are formed. 9 and 10 in the figure respectively represent an inter-element separating layer and insulating layer.
Inventors:
Takumi Nittono
Hirohiko Sugawara
Hiroshi Ito
Nagaaki Nakajima
Hitoshi Nagano
Hirohiko Sugawara
Hiroshi Ito
Nagaaki Nakajima
Hitoshi Nagano
Application Number:
JP13237293A
Publication Date:
August 12, 2002
Filing Date:
May 12, 1993
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
H01L29/205; H01L21/331; H01L29/73; H01L29/737; (IPC1-7): H01L21/331; H01L29/205; H01L29/737
Domestic Patent References:
| JP4102312A | ||||
| JP433372A | ||||
| JP5299340A | ||||
| JP5251460A | ||||
| JP5175226A |
Attorney, Agent or Firm:
Masaki Yamakawa
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