PURPOSE: To reduce code errors, by defining the modulation signal point arrangement as a gray code arrangement and by not using data of the first path for demodulation of the second path.

CONSTITUTION: The quad sum opearation between signals P11 and P12 of the first path is operated by a quad sum logical operation circuit 11. Meanwhile, the binary sum logic between signals P21 and P22 of the second path is operated by a binary sum logical operation circuit 12 ona basis of the relation to preceding output information only when signals P21 and P22 are 1 and 0 or 0 and 1 respectively. Outputs of the quad sum logical operation circuit 11 and the binary sum logical operation circuit 12 are combined in analogue adders 18 and 19 by addition and are applied to an orthogonal amplitude modulator consisting of phase modulators 20 and 21, a phase shifter 22, and a combining circuit 24. In the receiving side, the receiving signal is demodulated by an orthogonal amplitude demodulator and has a pulse signal separated through a level discriminating circuit and passes through a quad different logical operation circuit and a binary difference logical operation circuit to reproduce the first and the second path signals.