Title:
HIGH-SPEED COUNTER
Document Type and Number:
Japanese Patent JPH0722940
Kind Code:
A
Abstract:
PURPOSE: To obtain a high speed counter of which manufacturing and assembly are comparatively simple and economical by constituting the counter of a clock generator, a control circuit and a counting circuit and constituting the counting circuit of uniform delay structure having plural counter bit cells. CONSTITUTION: The high speed counter having the uniform delay structure is constituted of the clock generator 18, the control circuit 22 and the counting block 12. The uniform delay structure has plural counter bit cells each of which has its corresponding output bit and flip node and plural ladder networks each of which is operationally connected between the output of a bit cell and the flip node of a succeeding upper bit cell. The flip node of each counter bit cell responds to one corresponding ladder network, and when an evaluation signal is a high value, whether the flip node is to be maintained at a charged state or discharged is evaluated.
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Inventors:
PURANAI GAGURANI
Application Number:
JP4349494A
Publication Date:
January 24, 1995
Filing Date:
March 15, 1994
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INC
International Classes:
H03K23/44; H03K23/00; (IPC1-7): H03K23/00
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)
Next Patent: CLOCK REGENERATING DEVICE