Title:
不揮発性メモリの消去方法
Document Type and Number:
Japanese Patent JP4490630
Kind Code:
B2
Abstract:
A method of stably and uniformly erasing a non-volatile memory or memory array in a gate insulator in which carrier-trapping sites for carrier storage are furnished is described. A first method of the invention is the application of a discharge pulse(s) to a gate after erasure where the discharge pulse(s) discharges unstable holes injected into the gate insulator. A second method of the invention is injection of electrons into the trap sites of all the cells in a memory array to be erased before erasure. This makes Vth distribution across the memory array uniform after erasure. A third method of the invention is a reduced bias approach to erase stably the electrons stored in the trap sites. This includes not only literally "erase," but also "annihilate or neutralize" trapped electron charge by hole charge.
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Inventors:
Yutaka Hayashi
Ogura
Tomoya Saito
Ogura
Tomoya Saito
Application Number:
JP2002570309A
Publication Date:
June 30, 2010
Filing Date:
December 28, 2001
Export Citation:
Assignee:
Halo LSI Inc.
International Classes:
H01L21/8247; G11C16/02; G11C16/14; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JPH1174389A | 1999-03-16 | |||
| JP2001024075A | 2001-01-26 | |||
| JPH11297860A | 1999-10-29 | |||
| JPH06350098A | 1994-12-22 | |||
| JPH05258583A | 1993-10-08 |
Attorney, Agent or Firm:
Isono Dozo
Etsuo Tada
Etsuo Tada