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Patent Searching and Data


Title:
CONTROL METHOD FOR EQUIPMENT HAVING PLURAL PROCESSORS
Document Type and Number:
Japanese Patent JPH0652128
Kind Code:
A
Abstract:

PURPOSE: To shorten time until a system becomes an operable state from time when power is supplied by permitting main CPU to supply data to sub-CPU before the inspection of all storage areas in main RAM terminates and permitting sub-CPU to operate in accordance with data.

CONSTITUTION: When power is supplied, main CPU 11 inspects the lowermost area required for the basic operation of main CPU 11 in main RAM 12. Then, data deciding the operation mode of sub-CPU 21 is read from nonvolatile RAM 17. Then, main CPU 11 transmits operation mode decision data to sub-CPU 21 through an inter-CPU interface means 14. A remaining part which is not inspected in main RAM 12 is inspected. When abnormality is not detected, main CPU 11 is initialized and whether the initialization of sub-CPU 21 is terminated or not is checked. When the initialization of sub-CPU 21 is terminated, a regular operation is started.


Inventors:
SASAKI ICHIRO
Application Number:
JP22469092A
Publication Date:
February 25, 1994
Filing Date:
July 30, 1992
Export Citation:
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Assignee:
BROTHER IND LTD
International Classes:
G06F1/24; G06F15/16; G06F15/177; (IPC1-7): G06F15/16; G06F1/24
Attorney, Agent or Firm:
Yasuo Itaya