Title:
【発明の名称】面内の熱膨張率勾配を有するパッケージリッドを用いてパッケージの信頼性を高める方法
Document Type and Number:
Japanese Patent JP2000503488
Kind Code:
A
Abstract:
A package for mounting an integrated circuit chip includes a body having at least a first region, the size of the integrated circuit chip, and a second region. The first region has a first coefficient of thermal expansion (CTE), and the second region has a second, different CTE. The first region approximately matches the CTE of the integrated circuit chip mounted on the package, and the second region approximates the CTE of the printed wiring board to which the package is mounted.
Inventors:
Sylvester, Mark F.
Application Number:
JP52146498A
Publication Date:
March 21, 2000
Filing Date:
October 17, 1997
Export Citation:
Assignee:
W.L. GORE & ASSOCIATES, INCORPORATED
International Classes:
H01L23/29; H01L23/055; H01L23/14; H01L23/31; H01L23/373; H01L23/498; H05K1/02; (IPC1-7): H01L23/29; H01L23/14; H01L23/31
Attorney, Agent or Firm:
Takashi Ishida (4 others)