Title:
IC TESTER
Document Type and Number:
Japanese Patent JP3098700
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve the throughput of the test time by shortening the interleave correcting time when writing/reading the pass/fail data into/from a fail memory via an interleaving action at a high speed.
SOLUTION: Common uninterleaved addresses are fed to multiple fail memories 56a-57d by an address feeding means, and the logical sum signal of multiple pass/fail data outputted separately is outputted from a logical sum means. Pass/fail data are concurrently written into multiple fail memories 57a-57d based on the logical sum signal from the logical sum means by a writing means in the same cycle that the address feeding means feeds addresses. The same pass/fail data can be concurrently written into the multiple fail memories 57a-57d when the dispersedly stored pass/fail data are read out only once.
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Inventors:
Sei Isono
Application Number:
JP35190595A
Publication Date:
October 16, 2000
Filing Date:
December 27, 1995
Export Citation:
Assignee:
Hitachi Electronics Engineering Co., Ltd.
International Classes:
G01R31/28; (IPC1-7): G01R31/28
Domestic Patent References:
| JP4172268A | ||||
| JP9152470A | ||||
| JP519975U | ||||
| JP256760B2 |
Attorney, Agent or Firm:
Yoshihito Iizuka