To suppress increase of circuit size of a driving circuit accompanying multi-gradation.

A higher division resistance 26 produces higher gradation voltages v0 to v8M by equally dividing respective intervals of reference voltages VI0 to VIM for modulation circuit which are obtained by dividing a prescribed interval from non-light emission voltage VEOFF to largest light emission voltage VEON into equal M parts. A higher decoder part 41 selects a high voltage higher gradation voltage v1 and a low voltage higher gradation voltage v1+1 in accordance with data of higher J bits held by a data latch. A lower division resistance 43 produces gradation voltages v10 to vln-1 by equally dividing an interval between the selected high voltage higher gradation voltage v1 and the low voltage higher gradation voltage v1+1. A lower decoder part 44 selects and outputs an output voltage from a gradation voltage produced by a division resistance in accordance with data of lower K bits held by a data latch. Buffer amplitudes 42-1, 42-2 are provided between the lower division resistance 43 and the higher decoder part 41.