Title:
IMAGE FORMING DEVICE
Document Type and Number:
Japanese Patent JPS61272877
Kind Code:
A
Abstract:
PURPOSE:To process image information at a high speed by permitting alternately the 1st CPU to execute the error detection, correction, etc., of image information and the 2nd CPU to decode control data and write image data. CONSTITUTION:A system timing generator 32 generates a pulse signal with a 50% duty and supplies it to the 1st CPU 12 as a clock signal. During the H level of the clock signal, selectors 18 and 19 connect an address bus 16, an address decoder 17 and a data bus 13 to a RAM 15, and execute de-interleave processing and the error detection and error correction processing. The system timing generator 32 generates a pulse signal available from inverting the clock signal of the 1st CPU 12, and supplies it as a clock signal to the 2nd CPU 20. During the H level of the clock signal, the selectors 18 and 19 connect an address bus 23, an address decoder 24 and a data bus 21 to the RAM 15, and execute such processing as instruction decoding.
Inventors:
HIBINO CHITOSHI
ARIMOTO ATSUSHI
YOSHIHARA KENJI
ARIMOTO ATSUSHI
YOSHIHARA KENJI
Application Number:
JP11504585A
Publication Date:
December 03, 1986
Filing Date:
May 28, 1985
Export Citation:
Assignee:
VICTOR COMPANY OF JAPAN
International Classes:
G06F3/153; G06T11/00; G09G5/00; G09G5/39; G09G5/06; H04N9/804; H04N9/82; H04N9/877; (IPC1-7): G06F15/64; G06F15/72; G09G1/02
Attorney, Agent or Firm:
Tadahiko Ito