To provide an image processor which can perform such a processing as correcting movement of the hands on image data even when a memory of small capacity is used.

A D1-I/F 44a outputs a plurality of lines of pixel data from an SDRAM 26 and writes the pixel data in the plurality of memory blocks of an SDRAM 58 via a D1-I/F 44b. Buffer circuits 60 and 62 read out the pixel data periodically from the SDRAM 58, performs processing by a filter circuit 68, generates a plurality of lines of processed pixel data and writes the processed pixel data back to the plurality of memory blocks of the SDRAM 58 by buffer circuits 64 and 66. The memory block is set to ensure an offset between the writing start position via the D1-I/F 44b and the writing start position via the buffer circuits 64 and 66 so that overwrite is not performed in the memory block.

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