To improve the utilization efficiency of two or more provided accelerators when the image processing is performed by using two or more accelerators for processing the portion of the image processing processed in parallel in the hardware.

The actual address of a DMA buffer 50 is mapped into a common buffer region 70 on the continuous logical address space. A RIP processing section 90 inquires a DMA transmitting control library 30 of the emptied DMA buffer in the common buffer 70 and acquires it, and demands a device selection section 20 to perform the processing of continuing the writing of the intermediate data for passing the processing to an arbitrary accelerator 80. The device selection section 20 informs a driver 60 for controlling the arbitrary emptied accelerator 80 of the offset in the common buffer region 70 of the logical DMA buffer 33 notified from the RIP processing section 90, and issues the instruction for DMA transmitting of the intermediate data to the accelerator 80 and for processing the transmitted intermediate data.