To provide an image processor capable of segmenting an image and displaying the segmented image on a screen while suppressing an increase in cost and the deterioration of image quality as much as possible.

The image processor is provided with an A-D converter 12 for A-D converting an image signal outputted from a wide angle camera and outputting a digital signal, a clock generator 19 for generating the sampling clock of a digital image, an image segmentation setting means 24 for performing setting for segmenting a part of an analog image signal in the horizontal synchronizing signal section of the analog image signal, an image memory writing control part 18 for generating a write start signal and a write address on the basis of signals from the clock generator 19 and the segmentation setting means 24, an image memory 14 for storing the segmented image data, a clock generator 22 for generating a reading clock, reading address specification means 20, 21 for specifying an address of the image memory 14 on the basis of the clock, and a D-A converter 16 for D-A converting the image data read out from the image memory 14 in accordance with addresses specified by the reading address specification means 20, 21 and outputting analog data.