IMAGE REDUCTION METHOD AND DEVICE THEREOF

Title:

IMAGE REDUCTION METHOD AND DEVICE THEREOF

Document Type and Number:

Japanese Patent JP3763394

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To enable image data inputted into an image memory from a CPU to undergo a reduction process through a hardware so as to lighten a load imposed on a processing device such as the CPU.
SOLUTION: Two consecutive pixel data held at latches 41 and 42 are subjected to multiplication processing through multipliers 43 and 44, by the use of a coefficient Z generated by a multiplication coefficient generating circuit, and a complement of the coefficient Z generated by a complementer 45 and added up through an adder 45, so as to obtain new pixel data reflecting the inputted pixel data. A plurality of pixel data (block) outputted in parallel from a CPU 8 are converted into a serial form through an access adjustment circuit 40 and inputted into the latch 41 after they are shifted. On the other hand, the pixel data are delayed by one pixel data and inputted into the latch 42. The access adjustment circuit 40 holds the last pixel data of a block and consecutively joins them to the first pixel data of a following block. By this setup, even if the CPU 5 intermittently stops getting access to the image memory 5, pixel data are not interrupted between blocks.

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Inventors:

Toshiyuki Maekawa

Application Number:

JP2000333739A

Publication Date:

April 05, 2006

Filing Date:

October 31, 2000

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