Title:
【発明の名称】半導体集積回路及びそのテスト方法
Document Type and Number:
Japanese Patent JP3193394
Kind Code:
B2
Abstract:
PURPOSE:To minimize the increase of a logic scale for testing an interrupt control function and to improve the efficiency of a test design. CONSTITUTION:To an interrupt control circuit 10 which receives plural interrupt signals, arbitrates competing requests corresponding to the state of these signals and is capable of outputting the result, a testing register 11 alternately outputting a signal corresponding to part of the interrupt signal, that is, an interrupt element in which it is difficult to generate the interrupt, for example, or the interrupt element which may be deleted or added, is provided, by writing desired information in the testing register, the test of the interrupt control function can be enabled without depending on the operation of a function block corresponding to the signal to be alternated with. Since the testing register is provided so as to be restricted to partial interrupt signal, the increase of the logic scale of the circuit to be used only for the test can be minimized.
More Like This:
Inventors:
Naoki Mitsuishi
Application Number:
JP14382291A
Publication Date:
July 30, 2001
Filing Date:
May 20, 1991
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G06F11/22; G01R31/28; (IPC1-7): G06F11/22; G01R31/28
Domestic Patent References:
| JP357030A | ||||
| JP63188240A | ||||
| JP3109644A | ||||
| JP1236335A |
Attorney, Agent or Firm:
Tamamura Shizuyo