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Title:
INFORMATION WRITE/ERASION METHOD TO NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT
Document Type and Number:
Japanese Patent JPS54106139
Kind Code:
A
Abstract:

PURPOSE: To obtain a simple information write/erasion method by securing a fixed connection between the control gate, the source and the drain of the nonvolatile semiconductor memory using the floating gate type FET and then applying the fixed voltage to them.

CONSTITUTION: N-type source 2 and drain 3 are formed on P-type silicon substrate 1, and floating gate FG5 is provided via 1st insulator film 4. Then control CG6 is then provided on FG5 via 2nd insulator film 7. Thus, the nonvolatile semiconductor memory element is constituted. Drain 3 is connected to substrate 1 in earth potential VSS, and the voltage of 25W30V is applied to CG6 by several ms. Thus, FG5 is electrified negatively, and threshold voltage Vt shifts in the positive direction to perform writing. When CG6 is connected to substrate 1 and either source 2 or drain 3 is opened while applying the voltage of 25W30V to the other by several μs, FG5 is electrified positively and voltage Vt shifts in the negative direction to secure the erasion state.


Inventors:
SAKAI TAKESHI
Application Number:
JP6739678A
Publication Date:
August 20, 1979
Filing Date:
June 01, 1978
Export Citation:
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Assignee:
SANYO ELECTRIC CO
International Classes:
G11C17/00; G11C16/04; H01L21/8247; H01L29/788; H01L29/792; (IPC1-7): G11C11/40; G11C29/00