Title:
情報処理装置、プロセッサ、プロセッサの制御方法、情報処理装置の制御方法、キャッシュメモリ
Document Type and Number:
Japanese Patent JP4376692
Kind Code:
B2
Abstract:
In a method for controlling a processor (10) which accesses information of a storage device (30) through cache memory (20), when reading information stored in a target address or an address range of the storage device (30), it is monitored whether there is an update access to the address or address range from another processor (10), and also the processor (10) is entered into a suspense status, which is released using the occurrence of the update access to the storage device (30) from another processor (10) as a trigger.
Inventors:
Masaki Ukai
Application Number:
JP2004135875A
Publication Date:
December 02, 2009
Filing Date:
April 30, 2004
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F9/52; G06F1/32; G06F9/30; G06F9/312; G06F9/34; G06F9/38; G06F9/46; G06F12/08; G06F15/16; G06F15/177
Domestic Patent References:
| JP5127996A | ||||
| JP11282815A | ||||
| JP2006500639A | ||||
| JP3164964A | ||||
| JP10124316A | ||||
| JP2001236226A |
Foreign References:
| WO2003058447A2 |
Attorney, Agent or Firm:
Yoshiyuki Osuga
Motoaki Hisagi
Motoaki Hisagi