Title:
INFORMATION PROCESSOR AND INTERRUPTION CONTROL METHOD
Document Type and Number:
Japanese Patent JP3956767
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To solve a problem of conventional interruption control for a system having a plurality of CPUs that setting of the output of interruption request signals has little flexibility because only a table specifying a CPU to be a target of an interruption processing for every cause of interrupts is provided.
SOLUTION: An information processor having a plurality of CPUs is provided with a first hierarchy table having individual interrupt flags and individual interrupt enabling flags for every cause of interrupts, and a second hierarchy table having general interrupt flags and general interrupt enabling flags for every group of causes of interrupts. The information processor refers to the first hierarchy table and the second hierarchy table to determine whether a CPU to be a target of an interruption processing and an interruption request signal are needed or not, and outputs the interruption request signal to the CPU to be a target of an interruption processing when output of an interruption request signal is needed.
Inventors:
Akira Furusawa
Satoshi Kobayashi
Kenichi Suzuki
Kenji Kaneko
Nakamura Ikuo
Satoshi Kobayashi
Kenichi Suzuki
Kenji Kaneko
Nakamura Ikuo
Application Number:
JP2002131721A
Publication Date:
August 08, 2007
Filing Date:
May 07, 2002
Export Citation:
Assignee:
ソニー株式会社
International Classes:
G06F9/46; G06F9/48; (IPC1-7): G06F9/46
Domestic Patent References:
| JP7175665A | ||||
| JP7334372A | ||||
| JP8083190A | ||||
| JP2293961A |
Attorney, Agent or Firm:
Yoshio Inamoto