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Title:
INFORMATION PROCESSOR
Document Type and Number:
Japanese Patent JPS5755451
Kind Code:
A
Abstract:

PURPOSE: To achieve system constitution with flexibility, by detecting that the operand section of an instruction word read out from a storage device is an even or odd number and designating the address mode.

CONSTITUTION: The instruction word system is used, which is set with the number of bits being a multiple of an even number for number of bits constituting the content in minumum unit for the address of a main storage device 5. The instruction word read out from the main storage device 5 is applied to an instruction word register 3, and the instruction is executed by decoding the operation section and the operand section. As a result of the operation section, if it is a jump instruction, a control circuit 2 detects if the operand is an even number, and if it is an even number, the content of the operand is applied to a program counter 1 and the jump instruction is executed with a normal address mode. On the other hand, if an odd number, the address designated at the operand is defined as n, and the content at the address (n-1) is read out and the jump instruction is executed with the indirect address mode.


Inventors:
SHIMIZU HIROKIMI
Application Number:
JP12921280A
Publication Date:
April 02, 1982
Filing Date:
September 19, 1980
Export Citation:
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Assignee:
CANON KK
International Classes:
G06F9/35; G06F9/32; G06F9/34; G06F9/355; (IPC1-7): G06F9/30; G06F9/32; G06F9/36
Domestic Patent References:
JPS50100940A1975-08-11
JPS5414650A1979-02-03