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Title:
INPUT INTERRUPT DETECTION CIRCUIT, COMMUNICATION EQUIPMENT AND INPUT INTERRUPT DETECTION METHOD
Document Type and Number:
Japanese Patent JPH07193612
Kind Code:
A
Abstract:

PURPOSE: To stably attain input interruption with high reliability regardless of small scale configuration by monitoring logical combination of prescribed multi-bit digital demodulation signals so as to detect input interruption in a multi-value processing QAM communication equipment.

CONSTITUTION: A sent multi-value processing QAM signal is demodulated into a multi-bit digital demodulation signal having a most significant bit D1 indicating a sign and a bit D2 representing an amplitude and succeeding to the bit Di. The combination of logical values of the bits D1, D2 of the demodulation signal is monitored for a predetermined period by an exclusive logic arithmetic circuit 1 to be used for detecting input interruption and a discrimination circuit 2 raises an alarm. The circuit detects input interruption stably with high reliability through small scale configuration integrated in a digital demodulation circuit capable of being LSI-integrated independently of an analog level of an input signal without mis-discrimination of input interruption regardless of reception of erroneous data resulting from discrimination of presence of input even when OR result is lost at once.


Inventors:
IWAMATSU TAKANORI
AIKAWA SATOSHI
AKINAGA KOSHIRO
Application Number:
JP33389493A
Publication Date:
July 28, 1995
Filing Date:
December 27, 1993
Export Citation:
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Assignee:
FUJITSU LTD
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H04L27/00; H04L27/38; (IPC1-7): H04L27/38; H04L27/00
Attorney, Agent or Firm:
Tadahiko Ito



 
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