To make configuration suitable for IC by reducing circuit scale and saving power consumption.

A sampling system signal (a) is applied to coefficient equipment 55-57 and a sampling system signal (b) is delayed just for T/2 by a delay element 68 and applied to coefficient equipment 58-60 later. Thus, the outputs of coefficient equipment 55-60 can be added by a pipelined adder circuit 90 for which an adder and the delay element are alternately serially connected. At the time of 1st adding processing due to the pipelined adder circuit 90, registers 61-66 select tap coefficients C3-C5 and D3-D5 but at the time of 2nd adding processing, those registers select tap coefficients C0-C2 and D0-D2. Thus, all the tap coefficients are set to the coefficient equipment and the desired transversal filter output can be provided.