INSTRUCTION CONTROL MECHANISM OF PROCESSOR

Japanese Patent JP3781519

B2

PROBLEM TO BE SOLVED: To obtain the instruction control mechanism of a processor which can execute a set of instruction codes enabled to represent many kinds of instruction codes with short codes.
SOLUTION: This instruction control mechanism is equipped with an instruction decoder 45, a register 55, a storage circuit 56 which stores instantaneous values, and an arithmetic circuit and executes instruction codes each consisting of an instruction field, a 1st operand field, and a 2nd operand field. In this case, the mechanism is equipped with a register instruction detecting circuit 43 which allows a register instruction code having a register entered into its 2nd field to have a specific value in its instruction filed and a 2nd instruction field entered into the rest of the 2nd field, allocates the same value to the instruction field and 2nd instruction field of an instantaneous value instruction code and an instantaneous value similar register instruction code having the same process contents, and decides a specific value and a selecting circuit 44 which inputs one of the instruction field and 2nd instruction field to an instruction decoder according to the decision result.

WO/2023/211325	SECURE ROLLBACK OF SOFTWARE FAULT ISOLATION DOMAINS
JP2826927	[Title of Invention] Arithmetic processing unit and processing method
WO/2023/172660	HIGHLY PARALLEL PROCESSING ARCHITECTURE WITH OUT-OF-ORDER RESOLUTION

Shunsuke Kamijo

JP22408197A

May 31, 2006

August 20, 1997

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富士通株式会社

G06F9/30; G06F9/318; (IPC1-7): G06F9/30; G06F9/30

JP4283833A
JP3116230A
JP4319729A
JP6119168A
JP895783A

Takashi Ishida
Shigeru Tsuchiya
Toshio Toda
Masaya Nishiyama

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