PURPOSE: To ensure a free alteration of architecture, addition of new instruction and alteration of instruction, by constituting an instruction word deciphering device of an information processor with a random access memory.

CONSTITUTION: The instruction word read out of the main storage device 1 via the control part 2 is held in the instruction word holding register 3. The address of deciphering device 5 of a random access memory has the contents of the operational code 3 of register 3, and the read output of said device 5 is led to the AND circuit 6 and the control signal line 7. Other contents of register 3 are also led to the circuit 6. The contents of architectures A, B and C containing a detection of the wrong instruction type of instruction word, a control indication for groth of address and an operand fetch control indication in the form of information are read into said device 5 from the loader 9 via the address line 10 and data line 11 to secure an operation by the contents of said device 5.