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Title:
INSTRUCTION WORD TAKING-OUT SYSTEM IN DATA PROCESSOR
Document Type and Number:
Japanese Patent JPS5657146
Kind Code:
A
Abstract:

PURPOSE: To reduce the cost according to reduction of the number of words of a program and improve the execution speed, by taking out selectively instruction words which are stored in the main storage device and the rewritable associative storage device.

CONSTITUTION: The micro word taken out from control storage device 1 or rewritable associative storage device 2 is set to read register 3. Next, the micro instruction field of this micro word is sent to micro instruction register 4, and the address or contents of the field including the associative key are sent to retrieval register 5. The micro instruction of register 4 is decoded by micro instruction decoder 7, and switching signal D1 is sent to switching circuit 8. Contents of the retrieval register and the status register are sent to micro address register 9 or associative pattern register 10 by signal D1. The next micro word is taken out from device 1 when the address is set to register 9, and otherwise, the next micro word is taken out from device 2 when the associative key is set to register 10.


Inventors:
TAKAHASHI ETSUO
Application Number:
JP13179379A
Publication Date:
May 19, 1981
Filing Date:
October 15, 1979
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F9/22; G06F9/26; G06F9/32; G06F12/00; G06F12/06; G06F13/00; (IPC1-7): G06F9/26; G06F9/32; G06F13/00



 
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