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Title:
INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS62200819
Kind Code:
A
Abstract:

PURPOSE: To improve the output waveform while satisfying the compatibility with the standard ECL by providing a differential amplifier circuit as an output drive circuit and a means generating a termination voltage at the inside of the titled device.

CONSTITUTION: An internal logic circuit 1 has a ground electrode 2 and a power electrode 3 and connected with a pair differential switches FETs 4, 5 constituting a differential amplifier circuit and a current source FE6 specifying the circuit current respectively. A signal from the internal logic circuit 1 is outputted via the differential amplifier circuit comprising FETs 4, 5, 6. Since a resistor 7 and a diode 8 constitute a constant voltage generating circuit as a termination potential generation circuit, a -0.8V being an H level of the standard ECL is outputted while termination resistors 13, 14 are connected between output terminals 11, 12 and a termination potential supply terminal 10.


Inventors:
HIRAYAMA HIROMITSU
Application Number:
JP4166586A
Publication Date:
September 04, 1987
Filing Date:
February 28, 1986
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L21/8222; H01L27/06; H03K17/04; H03K19/0175; H03K19/0185; (IPC1-7): H01L27/08; H03K17/04; H03K19/00
Attorney, Agent or Firm:
Suzuki Akio



 
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