Title:
INTEGRATED CIRCUIT HAVING FUNCTION TESTING MEMORY USING VOLTAGE FOR STRESS AND ITS MEMORY TEST METHOD
Document Type and Number:
Japanese Patent JP3804733
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain an integrated circuit having a function testing a memory using voltage for stress by applying voltage for stress to a memory at the time of BIST only with simple logic.
SOLUTION: A supply voltage generating section of an integrated circuit clamps a level of internal supply voltage generated spontaneously responding to a control signal C, and outputs voltage for stress of internal supply voltage having a level being not clamped as supply voltage of a semiconductor memory. A stress control section 30 outputs a control signal C responding to an incorporated self-test BIST request signal BISTS and an input stress test signal from the outside. A BIST section 38 applies a signal for testing whether a semiconductor memory is defective or not to a semiconductor memory, responds to an output signal from a semiconductor memory D0 in accordance with an applied signal. The BIST request signal BISTS is generated in the semiconductor memory at the time of BIST, a stress test signal is inputted at the time of testing the semiconductor memory by applying voltage for stress to the semiconductor memory.
Inventors:
Lee Tetsuka
Application Number:
JP28167798A
Publication Date:
August 02, 2006
Filing Date:
October 02, 1998
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G01R31/28; G01R31/26; G11C29/06; G11C5/14; G11C29/12; G11C29/50; (IPC1-7): G11C29/00; G01R31/28
Domestic Patent References:
| JP8315598A | ||||
| JP6119776A | ||||
| JP6213977A | ||||
| JP9245498A | ||||
| JP10010204A |
Attorney, Agent or Firm:
Yasunori Otsuka
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