INTEGRATED CIRCUIT AND ITS PREPARATION - SGS THOMSON MICROELECTRONICS

Title:

INTEGRATED CIRCUIT AND ITS PREPARATION

Document Type and Number:

Japanese Patent JPH07221194

Kind Code:

A

Abstract:

PURPOSE: To manufacture an integrated circuit having a specific line width of less than one micron by forming a self-aligned contact by using an Si3 N4 insulating film having a reflection preventing effect. CONSTITUTION: A hole is opened by etching through a nitride layer 214 at a position where a contact to a fist polysilicon layer 210/212 deposited on a field oxide film 202 is formed. After an oxide film 216 is grown, Si3 N4 is conformably deposited thereon and is anisotropically etched by an SF6 +CF4 etching material while detecting edges to form a side wall spacer 220. A substance having a BPSG232 is deposited on an undoped silica glass 230 and then is etched by an oxide etching material having selectivity for Si3 N4 . This can control the line width below 0.5 micron.

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Inventors:

ROI ENU NIYUUEN
ROBAATO ERU HOTSUJI

Application Number:

JP31470094A

Publication Date:

August 18, 1995

Filing Date:

December 19, 1994

Export Citation:

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Assignee:

SGS THOMSON MICROELECTRONICS

International Classes:

H01L21/302; H01L21/3065; H01L21/336; H01L21/60; H01L21/768; H01L21/8234; H01L27/088; H01L29/78; (IPC1-7): H01L21/8234; H01L21/3065; H01L21/336; H01L21/768; H01L27/088; H01L29/78

Attorney, Agent or Firm:

Kazuo Kobashi (1 person outside)

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