Title:
INTERCONNECTION MEMORY
Document Type and Number:
Japanese Patent JPH07321820
Kind Code:
A
Abstract:
PURPOSE: To obtain a matrix memory device in which a command logic circuit is constituted so as to occupy only a minimum area in the total area of a memory by constituting a temporary interconnection point by a switching memory. CONSTITUTION: A 1st control means S [j, m], 24a, 24b virtually connects the writing port Din of at least one specified switching memory FIFOm (1<=m<=N3) among N3 switching memories 17 to be used as first in first out(FIFO) devices to a specified input bus among N1 input bus Rj (1<=j<=N1). A 2nd control means Sum, k] 24a', 24b' virtually connects at least one output bus out of plural output buses Ck (1<=k<=N2) to the reading port Dout of the switching memory FIFOm. The switching memory constitutes a temporary interconnection point independently of an input bus and an output bus to be interconnected.
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Inventors:
JIERARUDO SHIYOBERU
Application Number:
JP5618695A
Publication Date:
December 08, 1995
Filing Date:
March 15, 1995
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC
International Classes:
G06F15/16; G06F15/167; G11C7/00; G11C8/00; H04L12/56; H04Q3/00; H04Q11/04; (IPC1-7): H04L12/28; G06F15/163; G11C7/00; G11C8/00; H04Q3/00
Attorney, Agent or Firm:
Akira Asamura (3 outside)
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