Title:
INTERFACE CIRCUIT, SOURCE DRIVER, AND DISPLAY DEVICE
Document Type and Number:
Japanese Patent JP2022086246
Kind Code:
A
Abstract:
PURPOSE: To enable detection as to whether a data supply line is disconnected even when a plurality of drivers are in cascade connection.CONSTITUTION: An interface circuit includes: a timing signal generation circuit that generates a timing signal representing a switching timing of a data input period and a non-input period; a plurality of driver abnormality detection circuits that detect the abnormality occurring in a source driver; a selection circuit that selects one of the driver abnormality detection circuits in the non-input period and outputs a driver abnormality detection signal representing the abnormality detection result; an input abnormality detection circuit that detects the input abnormality of the data signal and outputs the input abnormality detection signal representing the result; an OR circuit that outputs the logical OR of the driver abnormality detection signal and the input abnormality detection signal; and a signal output unit including a MOS transistor whose gate terminal is connected to an output unit of the OR circuit and source terminal is connected to a predetermined potential and a signal output line connected to a drain terminal thereof.SELECTED DRAWING: Figure 3
Inventors:
WATABE YUKINOBU
Application Number:
JP2020198152A
Publication Date:
June 09, 2022
Filing Date:
November 30, 2020
Export Citation:
Assignee:
LAPIS TECH CO LTD
International Classes:
G09G3/36; G02F1/133; G09G3/20; H01L27/32; H01L51/50; H05B45/60
Attorney, Agent or Firm:
Patent Business Corporation Lexto International Patent Office