Title:
バーストモードをサポートする外部メモリとプロセッサとのインタフェース方法
Document Type and Number:
Japanese Patent JP4322116
Kind Code:
B2
Abstract:
Multiple data devices (A,B,C) are interfaced via a bus arbiter (S) with an external memory (F) so as to support burst-mode access by each device (A,B,C) one or more read registers (R1,R2,R3) are provided in the memory (F), and each register (R1,R2,R3) supports burst-mode access by a corresponding device (A,B,C). The arbiter (s) selects the register to be used following the initial access burst, according to the device requiring access. Thus, the memory (F) supports multiple burst-mode accesses in parallel.
Inventors:
Herzog, Eugene Pascal
Application Number:
JP2003529329A
Publication Date:
August 26, 2009
Filing Date:
September 17, 2002
Export Citation:
Assignee:
Mstar Semiconductor, Inc.
Mstar France S.A.S.
MStar Software R&D (Shenzhen) Limited
Mstar Semiconductor, Inc.
Mstar France S.A.S.
MStar Software R&D (Shenzhen) Limited
Mstar Semiconductor, Inc.
International Classes:
G06F12/02; G06F12/00; G06F13/16; G06F13/28; G06F13/30; G11C16/02; G11C16/06
Domestic Patent References:
| JP2002319292A | ||||
| JP2001014840A | ||||
| JP8063354A |
Attorney, Agent or Firm:
Yoshiyuki Kawaguchi
Hidemi Matsukura
Mayuko Wakuda
Katsuhiko Imahori
Hidemi Matsukura
Mayuko Wakuda
Katsuhiko Imahori