To provide an intermediate substrate in which difference of the linear expansion coefficient from the semiconductor integrated circuit element side can be reduced sufficiently for all terminals on the intermediate substrate and circuit discontinuity due to thermal stresses is prevented.
The intermediate substrate 200 comprises a substrate core 100 consisting of a core body section 100m formed planarly of a polymer material and having a sub-core containing part 100h opened in the first major surface to reduce its own thickness, and a ceramic sub-core section 1 formed planarly of ceramic and contained in the sub-core containing part 100h while aligning the thickness direction with the core body section 100m. The first terminal array 5 of the substrate core 100 is formed in such a positional relation as it is superposed on the ceramic sub-core section 1 in the orthogonal projection to a reference plane parallel with the plane surface of the substrate core 100. Furthermore, a first electrode conductor layer 54 conducting to a first side first class terminal 5a and a second side first class terminal 7a, a ceramic layer 52 becoming a dielectric layer, and a second electrode conductor layer 57 conducting to a first side second class terminal 5b and a second side second class terminal 7b are laid periodically in this order to form a multilayer ceramic capacitor which is built in the sub-core section 1.
KIMURA YUKIHIRO
SUGIMOTO YASUHIRO
SUZUKI KAZUHIRO
| JP2000315622A | 2000-11-14 | |||
| JP2002204071A | 2002-07-19 | |||
| JP2000261124A | 2000-09-22 | |||
| JP2002068832A | 2002-03-08 | |||
| JP2000243873A | 2000-09-08 | |||
| JP2002100876A | 2002-04-05 |
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