PURPOSE: To maintain a high speed operation and to make an amplitude of an output pulse small, and also to reduce the power consumption by providing two transistors in addition to a clamp voltage generating circuit, so that an output signal can be driven at a high speed thereby.

CONSTITUTION: A pulse generating circuit 2 is constituted of a NAND gate and three inverters IA1, IA2 and IA3. Also, a pulse generating circuit 3 is constituted of a NOR gate and three inverters IB1, IB2 and IB3. The inverters IA1∼IA3 have a characteristic by which a fall operation only is delayed, respectively, and the inverters IB1∼IB3 have a characteristic by which a rise operation only is delayed. By these inverter constitutions, a desired pulse is obtained in a node A0 and a node B0. Operations of a transistor TP and TN are controlled by a voltage of a node A3 and B3, respectively, but both the transistors are not turned on simultaneously, therefore, the power consumption can be further curtailed.