To prevent the occurrence of illegal interruption by outputting an interruption release signal when address data coincide with each other and releasing the interruption processing of CPU.

When CPU 11 access to an I/O address 12, address data showing this accessed I/O address is outputted to an FIFO buffer 13. The FIFO buffer 13 sequentially stores address data showing the address read out by CPU 11. Then comparator 15 stores the pattern of a specific address and outputs the interruption release signal when the pattern of address data stored in the FIFO buffer 13 and the pattern of stored specific address data coincide with each other. In addition when the interruption release signal is outputted from the comparator 15, an interruption controller 16 releases the interruption of CPU 11.