To provide a circuit for detecting the jitter which can be composed of only binary digital processing circuits adapted to digital signals, reduces the entire circuit scale and the power consumption and raises the detection accuracy.

A phase comparator 11 detects the phase differences of delayed or advanced clock data extracted from transmission data, relative to the transmission data, a sampling circuit 13 samples the detected phase differences with a separate clock signal independent of a transmission data extraction clock generated from a system clock by a sampling clock signal generator circuit 16, an up-down counter 14 counts them, and a latch circuit 15 integrates them so that the detecting operation of the jitter of the transmission data extraction clock for the transmission data, based on the integrated value, can be realized by only a digital process handling binary signals.