Title:
LAND PATTERN FOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH05327197
Kind Code:
A
Abstract:
PURPOSE: To provide a land pattern for an integrated circuit of high quality in which an open malfunction of soldering to be effectively mounted electrically and in strength on a printed board of the circuit does not occur.
CONSTITUTION: A structure in which a slit 9 formed along a direction perpendicular to the direction of leads 11 is formed is provided at the center of a land pattern 8 to be fixed with leads of an integrated circuit 10 in a land pattern 8 for mounting the circuit 10 on a printed board 7. A sufficient amount of solder 12 remains between the pattern 8 and the leads 11 by dividing its flow at the slit 9 to rigidly fix the both.
Inventors:
MORIGUCHI SHIROU
Application Number:
JP15871292A
Publication Date:
December 10, 1993
Filing Date:
May 25, 1992
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L23/50; H05K3/34; H05K1/11; (IPC1-7): H05K3/34
Attorney, Agent or Firm:
Takashi Yamamoto