PURPOSE: To enhance the integration of an integrated circuit by alternately disposing wiring layers of multilayer low resistance metal in a direction perpendicular to a channel direction and a direction parallel thereto.

CONSTITUTION: The channel directions of P-channel MOS transistors 17, 18 and N-channel MOS transistors 19, 20 are X-direction, and aluminum wirings 4W9, 10W14, F of the first layer are disposed in Y-direction. Aluminum wirings A, B, C, D, E, G H, VCC and VSS of the second layers are disposed in X- direction, the electrodes of the transistors 17W30 and polycrystalline silicon layers 21W25 are connected through a contacting region 16 with aluminum wirings of the first layer, which is connected via a through hole 15 with the aluminum wirings of the second layer. When thus layed out, the transistors 17W20 can be formed under the aluminum wirings, and the channel lengths and widths of the transistors 17W20 are not limited in size, thereby setting them in the optimum size.