Title:
LAYOUT DEVICE, LAYOUT METHOD AND PROGRAM
Document Type and Number:
Japanese Patent JP2022143696
Kind Code:
A
Abstract:
To provide a layout device capable of reducing variations in signal propagation delay in a plurality of transmission lines without increasing the number of elements in a layout of an integrated circuit.SOLUTION: The layout device includes specification means for specifying a delay time of each of a plurality of transmission lines between a first circuit and a second circuit in a layout of an integrated circuit, reception means for receiving layout information in which the arrangement of at least one of the first circuit and the second circuit is changed based on the delay time specified by the specification means, and change means for changing at least one layout of the plurality of transmission lines based on the layout information received by the reception means.SELECTED DRAWING: Figure 3
Inventors:
SATO TAKANORI
BEPPU SACHIKO
BEPPU SACHIKO
Application Number:
JP2021044353A
Publication Date:
October 03, 2022
Filing Date:
March 18, 2021
Export Citation:
Assignee:
NEC PLATFORMS LTD
International Classes:
G06F30/39; H01L21/82
Attorney, Agent or Firm:
Sumio Tanai
Ryuichiro Mori
Yasushi Matsunuma
Eisuke Ito
Ryuichiro Mori
Yasushi Matsunuma
Eisuke Ito
Previous Patent: Shaft member fitting structure, its design method, and fretting fatigue test method
Next Patent: Preparative liquid chromatograph
Next Patent: Preparative liquid chromatograph