LAYOUT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

Title:

LAYOUT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

Document Type and Number:

Japanese Patent JPH0816649

Kind Code:

A

Abstract:

PURPOSE: To accurately design an integrated circuit for the standard cell or building block system of an analog system in a short time.

CONSTITUTION: This method is provided with a process A for performing logical design based on a specification, process B for performing circuit design at a transistor level based on this logical design, process C for preparing a symbol drawing at a microlevel based on this circular diagram information, process D for performing floor planning for arranging the blocks of macro assemblies of the chips of the assemblies of these blocks based on this symbol drawing, process E for performing macro layout based on the result of the process B, process G for arranging the chips of plural macro assemblies based on this layout, and process H for comparing the layout result from the process E to G with the result of the process D and performing correction when both the results are not matched.

More Like This:

JP2005175489	LOW POWER SEMICONDUCTOR CHIP HAVING SEPARATED POWER RING AND MANUFACTURE AND CONTROL METHOD OF THE SAME
JPH11134385	METHOD FOR INSPECTING FUNCTION OF LOGIC CIRCUIT AND CIRCUIT ALLOCATING DEVICE FOR INSPECTING FUNCTION
JP5446112	Semiconductor device and operation monitoring method for semiconductor device

Inventors:

NIIYAMA SHINYA

Application Number:

JP15096794A

Publication Date:

January 19, 1996

Filing Date:

July 01, 1994

Export Citation:

Click for automatic bibliography generation Help

Assignee:

FUJITSU LTD

International Classes:

H01L21/82; G06F17/50; (IPC1-7): G06F17/50; H01L21/82

Attorney, Agent or Firm:

Teiichi

Next Patent: LOGIC SYNTHESIZATION AND LAYOUT ARRANGEMENT WIRING DEVICE