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Title:
LAYOUT SYSTEM OF INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS59181049
Kind Code:
A
Abstract:

PURPOSE: To readily prevent a latchup by providing a direct part for applying the dame potential as a well through a polysilicon layer between the layer and a diffused portion by utilizing the layer used for wiring.

CONSTITUTION: 2-layer wiring polysilicon is regions 10, 11 which contains round marks, and an aluminum electrodes are regions 12, 12' indicated by rightward hatched lines (solid lines). A P+ type diffused region is a right hatched (broken lines) region 13, and an N+ type diffused region is a region 14 indicated by leftward hatched solid lines. A boundary line of N- type well is indicated by 1-dotted chain lines 16. The wirings of word line 1 are formed of 1-layer polysilicon, and wirings of bit lines 2, 3 are formed of aluminum electrodes 12, 12'. A power source voltage and ground potential are supplied by the potentials of the regions 13 and the region 11. The potential of the N- type well is similarly supplied by the potential of the region 11.


Inventors:
URATANI MUNEHIRO
Application Number:
JP5469483A
Publication Date:
October 15, 1984
Filing Date:
March 30, 1983
Export Citation:
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Assignee:
SHARP KK
International Classes:
H01L27/08; H01L21/8244; H01L27/11; H01L29/78; (IPC1-7): H01L27/08; H01L27/10; H01L29/78
Attorney, Agent or Firm:
Kazuhide Okada



 
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