LAYOUT VERIFICATION METHOD AND DESIGN METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING THE SAME

Title:

LAYOUT VERIFICATION METHOD AND DESIGN METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING THE SAME

Document Type and Number:

Japanese Patent JP2006140349

Kind Code:

A

Abstract:

To provide a layout verification method for a semiconductor integrated circuit device capable of detecting correctly a damage which a gate receives, and to provide a design method for the semiconductor integrated circuit device which enhances more sufficient workability and higher reliability, by determining the directivity for a design modification so as to avoid a plasma charging damage while detecting correctly the damage which the gate receives.

The layout verification method can output an antenna value as an estimated value of the transistor gate damage on the basis of the antenna rate and the change rate of a plasma charging damage caused by the layout in the vicinity of the transistor gate.

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Inventors:

ITO MASANORI
MUKAI KIYOSHI

Application Number:

JP2004329421A

Publication Date:

June 01, 2006

Filing Date:

November 12, 2004

Export Citation:

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Assignee:

MATSUSHITA ELECTRIC IND CO LTD

International Classes:

H01L21/82; H01L21/822; H01L27/04

Attorney, Agent or Firm:

Takeshi Takamatsu
Toshimitsu Ichikawa
Kimihide Hashimoto

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