PURPOSE: To enable reduction in power voltage of low voltage system without increasing a chip area for reducing an ON-resistance of an input transistor, in a level shifter circuit for liquid crystal display device.

CONSTITUTION: Resistances 7 and 8 formed with drift layer are inserted between PMOS transistors 1 and 2 connected to a low voltage system power voltage VDD and between NMOS transistors 3 and 4 connected to a high voltage system power voltage VEE, respectively. Even if an ON-resistance of the transistors 1 and 2 is increased by a reduction in VDD, a voltage level output into a next stage medium pressure-resistant logic part is adjusted by the resistances 7 and 8, and increase in current consumption due to reduction in response speed and increase in condition transient time can be prevented.