PURPOSE: To provide a PLL lock detecting circuit capable of detecting the lock with high accuracy even with a small phase difference obtained between a reference signal and a comparison signal.
CONSTITUTION: An EOR circuit 1 secures an exclusive OR between a reference signal 1a and a comparison signal 1b and detects a phase difference. The detected signal 1c and both signals 1a and 1b are defined as the data and the clocks and then inputted to 1st and 2nd D flip-flop circuits 2 and 3 respectively. These circuits 2 and 3 hold the data at the trailing edge of the clock, therefore only the fall phase difference between the signals 1a and 1b is detected. Then the output signals 2c and 3c are inputted to a NOR circuit 4. Thus a locking signal 4c is outputted so that a locking state and an unlocking state are secured when the fall phase are matched with each other and not matched with each other between both signals 1a and 1b respectively.
YOSHIDA NAOMI
TANIMOTO MASAYASU
TAJIMA KATSUTOSHI
ABE HITOSHI
IWAI MASAHIRO
HITACHI VIDEO & INF SYST
HITACHI COMPUTER ELECTRONIC