Title:
LOGIC CIRCUIT DESIGNING METHOD
Document Type and Number:
Japanese Patent JP2003186930
Kind Code:
A
Abstract:
To efficiently execute LSI design by applying signal transition time constraints decided for each master cell to an instance cell having a function similar to that of the master cell.
A plurality of different signal transition time constraints 125-128 are set at the input terminal of each reference logical element (master cell), and the signal transition time constraints 125-128 corresponding to the specifications of the reference element (master cell) are set at the input terminal of each logical element (instance cell) so that the driving capability of the logical element (instance cell) is adjusted.
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Inventors:
SHINJO SHINJI
Application Number:
JP2001382299A
Publication Date:
July 04, 2003
Filing Date:
December 14, 2001
Export Citation:
Assignee:
SHARP KK
International Classes:
G06F17/50; H01L21/82; (IPC1-7): G06F17/50; H01L21/82
Attorney, Agent or Firm:
Shusaku Yamamoto
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