PURPOSE: To eliminate a noise or malfunction due to the making of a circuit into one chip and to attain high performance and low cost.

CONSTITUTION: The sources of transistors N1-N4 are connected to a constant current source I. A clock signal CK is inputted to the gates of the transistors N1, N4, and a clock CKH complementary to the clock signal CK is inputted to the gates of the transistors N2, N3. An input signal D1 is inputted to the gate of a transistor N5, and an input signal DIN complementary to the input signal D1 is inputted to the gate of a transistor N8. The gate of a transistor N6 is connected to the drain of a transistor H7, and the gate of the transistor N7 is connected to the drain of the transistor N6. The drains of the transistors N5, N6 are connected to a power source VDD via a resistor R1, and the drains of the transistors N7, N8 are connected to the power source VDD via a resistor R2.