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Title:
LOGICAL CIRCUIT CONNECTION RULE VERIFICATION METHOD
Document Type and Number:
Japanese Patent JPH06195409
Kind Code:
A
Abstract:

PURPOSE: To attain a high speed processing by avoiding duplicated verification by obtaining information necessary for the verification of the connection rule of a hierarchical block on the high-order side of a hierarchical block and storing it at the time of verifying the connection rule of the hierarchical block.

CONSTITUTION: This method executes the step of verifying the connection rule with regard to a net closing inside of the hierarchical block successively from the hierarchical block on a lower side toward that on a higher side and the step of obtaining information necessary for the verification of the connection rule of the hierarchical block on the high-order side with regard to a net connected to the hierarchical block on the high-order side of the hierarchical block and storing it. Namely, this logical circuit connection rule verification method verifies the connection rule successively from the hierarchical block on the low-order side toward that on the high-order side and at the time of verifying the connection rule of a hierarchical block, the method obtains information necessary for the verification of the connection rule of the hierarchical block on the high-order side of the hierarchical block and stores it.


Inventors:
KONDO TAKEO
Application Number:
JP34420592A
Publication Date:
July 15, 1994
Filing Date:
December 24, 1992
Export Citation:
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Assignee:
KAWASAKI STEEL CO
International Classes:
G06F11/25; G06F11/26; G06F17/50; (IPC1-7): G06F15/60; G06F11/26
Attorney, Agent or Firm:
Yoshio Kosugi (1 person outside)