Title:
LOGICAL CIRCUIT
Document Type and Number:
Japanese Patent JP3855069
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a logical circuit which can execute FA command in a relatively simple configuration.
SOLUTION: A delta register 4 is prepared at the output side of an accumulator 3. First, data in FA queue 1 is transmitted to FA register 2. Next, a synchronous variable (semaphore) stored in a memory 6 and a value in the FA register 2 are transmitted to the accumulator 3. This operation is conducted only at the first time. And, an output of the accumulator 3 is stored in the delta register 4. Then, the second data in the FA queue 1 is transmitted to the accumulator 3. Meanwhile, data in the delta register 4 is also transmitted to the accumulator 3. Next, an output of the accumulator 3 is stored in the delta register 4. Furthermore, the same process is conducted for the data of the third and the further in the FA queue 1. When the FA queue 1 is empty or the data in the FA queue 1 accesses a different address from what it used be, the data in the delta register 4 is written back to the memory 6 as the synchronous variable.
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Inventors:
Taiichi Nakayama
Tatsuya Kawami
Tatsuya Kawami
Application Number:
JP2002026663A
Publication Date:
December 06, 2006
Filing Date:
February 04, 2002
Export Citation:
Assignee:
Campus Create Co., Ltd.
International Classes:
G06F9/34; G06F9/52; G06F9/30; G06F12/00; (IPC1-7): G06F9/34; G06F9/30; G06F12/00
Other References:
GOTTLIEB, A., et al.,Basic Techniques for the Efficient Coordination of Very Large Numbers of Cooperating Sequential Processors,ACM Transactions on Programming Languages and Systems(TOPLAS),ACM Press,1983年 4月,Vol. 5, Issue 2,pp. 164 - 189
Attorney, Agent or Firm:
Shigeo Naruse