To store generated data of a separate process to a RAM without being changed or overwritten by an interrupt process of higher priority, even if access is carried out simultaneously, when the RAM is shared by an interrupt process and a normal process in a load/store type microcomputer.
An address determination device 102 has a shared address area to be accessed from a plurality of processes, and sends a signal to a process priority determination device 105 when an address to be stored in a RAM 104 is contained in a shared address area. When receiving the signal from the address determination device 102, the process priority determination device 105 determines the level of priorities according to a kind of processing being performed. When the process being performed is determined to be a low priority process by the process priority determination device 105, an interrupt mask control unit 108 indicates the interrupt mask control unit 108 to mask the interrupt process.
ENAMI YASUHIKO
IWATA YOSHIHIRO
Toshimitsu Ichikawa
Kimihide Hashimoto