Title:
LOGICAL CIRCUIT
Document Type and Number:
Japanese Patent JPS5672534
Kind Code:
A
Abstract:
PURPOSE: To hold an output released and prevent an operation error at the time of transition, by grounding the input terminal which becomes the reverse logical polarity to the output of the logical gate, through the resistance.
CONSTITUTION: The input of the NAND gate 3 is held at a low level by resistance 2 at the time of transition when the electric power supply is closed and cut off. Accordingly, since the output of the NAND gate 4 is held at a high level, an operation error of the logical circuit can be prevented at the time of transition.
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Inventors:
ANDOU TETSUYA
NUNOTANI MASAKATSU
NUNOTANI MASAKATSU
Application Number:
JP14769779A
Publication Date:
June 16, 1981
Filing Date:
November 16, 1979
Export Citation:
Assignee:
HITACHI LTD
NIPPON TELEGRAPH & TELEPHONE
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H03K17/22; H03K19/003; (IPC1-7): H03K3/02