PURPOSE: To realize a high speed by the reduction of parasitic capacitance and to lower power consumption by the reduction of a through-current at the time of an operation.

CONSTITUTION: K pieces of the PMOS transistors Qp'<k> of a low threshold voltage are connected in parallel between a power supply Vcc and an output node OUT and K pieces of NMOS transistors Qn'<k> of a high threshold voltage are serially connected between the output node OUT and ground. Then, the gates of the NMOS transistors and the PMOS transistors whose drains are connected to the output node OUT in common are connected to an input terminal in common and a K input NAND gate is constituted.