Title:
LOGICAL SIMULATION METHOD AND LOGICAL SIMULATOR
Document Type and Number:
Japanese Patent JP3654941
Kind Code:
B2
Abstract:
PURPOSE: To suppress the increase of types of dummy elements by enabling a circuit designer to deal with the timing verification definition.
CONSTITUTION: A circuit file 2 stores the data on a logic circuit including a logic cell and a macro and also stores the timing verification definition of the macro requiring the timing verification. A library file 4 stores the timing verification definition or the logic cent requiring the timing verification. A dummy element generating part 11 fetches the macro timing verification definition corresponding to the macro pointed by the file based on the timing verification of a prescribed macro when the logical simulation is started for a designed logic circuit. Then the part 11 generates the data on the dummy elements based on the macro timing verification definition and adds this data to the logic circuit data. A processing unit 15 carries out the timing verification of the designed logic circuit.
Inventors:
Okumura Takamasa
Application Number:
JP1470995A
Publication Date:
June 02, 2005
Filing Date:
January 31, 1995
Export Citation:
Assignee:
富士通株式会社
富士通ヴィエルエスアイ株式会社
富士通ヴィエルエスアイ株式会社
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP5061931A | ||||
| JP6243191A | ||||
| JP6243192A | ||||
| JP6124319A |
Attorney, Agent or Firm:
Hironobu Onda
Previous Patent: COMMUTATION TICKET ISSUING MACHINE
Next Patent: PRODUCTION HYSTRESIS TRACKING DEVICE
Next Patent: PRODUCTION HYSTRESIS TRACKING DEVICE