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Patent Searching and Data


Title:
LOGICAL SIMULATION METHOD
Document Type and Number:
Japanese Patent JPH04243482
Kind Code:
A
Abstract:

PURPOSE: To make a period of time for propagating signals from an element having a plurality of fanouts shortest by enhancing the parallelism of propagation of a plurality of signals.

CONSTITUTION: A plural fanout element finding section 1 inputs circuit description to find an element having a plurality of fanouts. An additional presignal propagation time calculating section 2 calculates a period of time for signal propagation from a found element. An additional postsignal time calculating section 3 calculates a period of time for signal propagation from the found element, provided that a fanout split element is added between the found element and a fanout destination of the found element. A compare discriminating section 4 compares all of a set of propagation times for these signals to judge the number of fanout split elements to be added. A fanout split element adding section 5 adds an appropriate number of fanout split elements in to a relevant circuit. A connection change section 6 changes connection accompanied by the addition. An allocation section 7 allocates adding fanout split elements to different processors.


Inventors:
OKUBO ICHIRO
Application Number:
JP411891A
Publication Date:
August 31, 1992
Filing Date:
January 18, 1991
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F11/25; G06F11/26; G06F17/50; G06F19/00; (IPC1-7): G06F11/26; G06F15/20; G06F15/60
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)